• Operates from ±5 V to ±18 V supplies
• Less than 10 ms acquisition time
• TTL, PMOS, CMOS compatible logic input
• 0.5 mV typical hold step at CH = 0.01 mF
• Low input offset
• 0.002% gain accuracy
• Low output noise in hold mode
• Input characteristics do not change during hold mode
• High supply rejection ratio in sample or hold
• Wide bandwidth